Journal of Modern Power Systems and Clean Energy

ISSN 2196-5625 CN 32-1884/TK

FPGA-based Digital Implementation of Flexible Power Control for Three-phase to Single-phase MMC-based Advanced Co-phase Traction Power Supply System
Author:
Affiliation:

1.National Rail Transportation Electrification and Automation Engineering Technology Research Center, Chengdu 611756, China
2.School of Electrical Engineering, Southwest Jiaotong University, Chengdu 611756, China
3.Department of Electrical Engineering, City University of Hong Kong, Hong Kong, China
4.School of Electrical Engineering and Automation, Wuhan University, Wuhan 430072, China
5.Department of Electrical Engineering, Tsinghua University, Beijing 100084, China
6.Department of Energy Technology, Aalborg University, Aalborg 9220, Denmark

Fund Project:

This work was supported in part by the National Rail Transportation Electrification and Automation Engineering Technology Research Center (No. NEEC-2019-A04), in part by the National Key R&D Program of China (No. 2021YFB2601500), in part by the National Natural Science Foundation of China (No. 52077183), and the National Science Foundation for Young Scientists of China (No. 52207138).

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    Abstract:

    A three-phase to single-phase modular multilevel converter based advanced co-phase traction power supply (MMC-ACTPS) system is an effective structure to address the concerns of phase splitting and poor power quality of the conventional electrified railway. Due to the large number of MMC-ACTPS system modules, I/O resources and computing speed have high requirements on processors. Moreover, the module capacitor balance is challenging because the sorting time is too long when the traditional sorting algorithm for voltage balance is used. To solve the above issues, a digital implementation scheme of flexible power control strategy for three-phase to single-phase MMC-ACTPS system based on field programmable gate array (FPGA), which has sufficient I/O resources, has been proposed. Due to the parallel execution characteristics of the FPGA, the execution time of the controller and the modulator can be greatly reduced compared with a digital signal processor (DSP) + FPGA or DSpace. In addition, an improved sorting algorithm is proposed to reduce the sorting time and the implementation steps are analyzed. Finally, simulation and experimental results are presented to demonstrate the effectiveness and correctness of the proposed control strategy.

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History
  • Received:October 25,2022
  • Revised:December 17,2022
  • Adopted:
  • Online: November 16,2023
  • Published: